(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technology useful for efficient rearrangement of an external connecting terminal in a wafer level package having a plurality of devices fabricated therein.
(b) Description of the Related Art
A semiconductor device (or chip) such as an IC or an LSI for use in electronic equipment or apparatuses has recently become higher in packaging density and thus larger in capacity accompanied by an increase in the need for miniaturization and high performance of the electronic equipment or apparatuses. A package for mounting a semiconductor chip, in turn, has also been designed to be more compact (or slimmer), greater in the number of pins, higher in density, and so on. Also, an MCP (multi chip package) having a plurality of semiconductor chips mounted on a substrate has come into practical use, and in particular, a stack-type MCP is in general use. Moreover, a technology for further miniaturization, such as a CSP (chip size package), is required for mounting semiconductor chips.
For a package for mounting a plurality of semiconductor devices (i.e., active devices), the utilization of a wafer level package enables the formation of fine wiring, and hence makes a contribution to an increase in density or the like. In a typical wafer level package, an insulating film is made of a passivation film, a polyimide resin or the like, and is formed as a protection film on a surface of a wafer into which devices are fabricated; the insulating film having an opening is formed in a desired position therein; a conductor layer (i.e., a rewiring layer) is formed on the insulating film, and allows an electrode pad (i.e., a wiring layer) of each of the devices to communicate with the outside of the package through the opening of the insulating film; a conductor post is further disposed on the rewiring layer in a portion where a terminal is formed; the entire surface of the wafer on which the conductor post is formed is encapsulated with an encapsulation resin (but so as to expose the top portion of the conductor post to the outside); and the top portion of the conductor post is bonded to an external connecting terminal (e.g., a solder ball or the like).
One example of the technologies related to the above conventional technology is disclosed in Japanese unexamined Patent Publication (Kokai) 2002-237567. In a stack-type MCP (semiconductor device) disclosed in this publication, leads (stitches) or wirings are formed on the surface of an insulating layer of a substrate in which a semiconductor chip is encapsulated. The stitches include: stitches connected to pad electrodes by bonding wires on the semiconductor chip; and extra stitches disposed on the surface of the insulating layer.
As mentioned above, for the package for mounting the plurality of semiconductor devices, the utilization of the wafer level package enables the formation of fine wiring. Meanwhile, for rearrangement (i.e., the rearrangement of the external connecting terminal) on the wafer level, wiring formation (i.e., rewiring) in a single layer of conductors is desirable in terms of cost.
However, conductors are divided into wirings of different attributes, such as a power supply line for feeding a desired power supply voltage to each device, a ground line, and a signal line for conveying data, a control signal or the like. Furthermore, even the signal lines of the same attribute include various wirings, such as a wiring for 5 V and a wiring for 3.3 V, according to a supply voltage. Likewise, even the signal lines of the same attribute include various wirings, such as a wiring for an analog signal and a wiring for a digital signal, according to a type of signal. Thus, if the conductors (i.e., the wirings) are designed under constraints (e.g., line/space, etc.) on connection information, design, or the like that conflict with each other, a problem can possibly arise in that rewiring in a single layer of conductor becomes impossible regardless of the number of pins (i.e., the number of external connecting terminals installed) of the package.